**** * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I I I I I I I * * I I I I I I I I I **** I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I DIRECT ADDRESS BIT I I I * * I F7 I F6 I F5 I F4 I F3 I F2 I F1 I F0 I * * I I I I I I I I I **** * *** *** * * * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I I I I I I I * * * * I I I I I I I I I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I DIRECT ADDRESS BIT I I I *********** * * I E7 I E6 I E5 I E4 I E3 I E2 I E1 I E0 I * * * * * * I I I I I I I I I * * *** *** ***** **** * * * * * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * I C I AC I F0 I RS1 I RS0 I OV I - I P I * * * * * I I I I I I I I I ***** * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * I I I DIRECT ADDRESS BIT I I I * * * * * * I D7 I D6 I D5 I D4 I D3 I D2 I D1 I D0 I * * * * * * * I I I I I I I I I * **** ** ** PSW.7 -> D7 - C = CARRY PSW.6 -> D6 - AC = AUXILIARY CARRY PSW.5 -> D5 - F0 = CUSTOMIZING FLAG PSW.4 -> D4 - RS1 = REGISTER SELECT BANK 1 PSW.3 -> D3 - RS0 = REGISTER SELECT BANK 0 _______________________________________ I RS1 I RS0 I N bank I ADDRESS REGION I I_____I_____I________I________________I I 0 I 0 I bank 0 I 00 - 07 I I 0 I 1 I bank 1 I 08 - 0F I I 1 I 0 I bank 2 I 10 - 17 I I 1 I 1 I bank 3 I 18 - 1F I I_____I_____I________I________________I PSW.2 -> D2 - OV = OVERFLOW PSW.1 -> D1 - = RESERVED BIT PSW.0 -> D0 - P = PARITY =================================== INTERRUPT PRIORITY REGIGISTER =================================== IP.4 -> PS = SERIAL PORT INTERRUPT PRIORITY LEVEL.PS=1 HIGHER PRIPRITY LEVEL IP.3 -> PT1= TIMER 1 INTERRUPT PRIORITY LEVEL.PT1=1 HIGHER PRIORITY LEVEL IP.2 -> PX1= EXTERNAL INTERRUPT 1 PRIORITY LEVEL.PX1=1 HIGHER PRIORITY LEVEL IP.1 -> PT0= TIMER 0 INTERRUPT PRIORITY LEVEL.PT0=1 HIGHER PRIORITY LEVEL IP.0 -> PX0= EXTERNAL INTERRUPT 0 PRIORITY LEVEL.PX0=1 HIGHER PRIORITY LEVEL ***** ***** * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * I - I - I - I PS I PT1 I PX1 I PT0 I PX0 I * * * I I I I I I I I I * ***** I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I DIRECT ADDRESS BIT I I I * * I - I - I - I BC I BB I BA I B9 I B8 I ***** * I I I I I I I I I SOURCE VECTOR ADDRESS ------ -------------- IE0 3 0003 H EXTERNAL INTERRUPT 0 TF0 11 000B H TIMER 0 IE1 19 0013 H EXTERNAL INTERRUPT 1 TF1 27 001B H TIMER 1 RI + TI 35 0023 H SERIAL PORT INTERRUPT ======================================= INTERRUPT ENABLE REGISTER ======================================= __ IE.7 -> EA = DISABLES ALL INTERRUPTS. EA = 0 -> NO INTERRRUPT WILL BE ACKNOWLIEDGED, INDEPENDED FROM IE.4 - IE.0 STATUS. EA = 1 -> EACH INTERRUPT SOURCE IS INDIVIDUALLY ENABLED OR DISABLED BY SETTING OR CLEARING ITS ENABLE BIT. IE.4 -> ES = ENABLES OR DISABLES THE SERIAL PORT INTERRUPT. ES = 0 -> THE SERIAL PORT INTERRUPT IS DISABLED BY RI OR TI ES = 1 -> THE SERIAL PORT INTERRUPT IS ENABLED BY RI OR TI IE.3 -> ET1 = ENABLES OR DISABLES THE TIMER 1 OVERFLOW INTERRUPT. ET1= 0 -> THE TIMER 1 INTERRUPT IS DISABLED. ET1= 1 -> THE TIMER 1 INTERRUPT IS ENABLED. IE.2 -> EX1 = ENABLES OR DISABLES EXTERNAL INTERRUPT 1. EX1= 0 -> EXTERNAL INTERRUPT 1 IS DISABLED. EX1= 1 -> EXTERNAL INTERRUPT 1 IS ENABLED. IE.1 -> ET0 = ENABLES OR DISABLES THE TIMER 0 OVERFLOW INTERRUPT. ET0= 0 -> THE TIMER 0 INTERRUPT IS DISABLED. ET0= 1 -> THE TIMER 0 INTERRUPT IS ENABLED. IE.0 -> EX0 = ENABLES OR DISABLES EXTERNAL INTERRUPT 0. EX0= 0 -> EXTERNAL INTERRUPT 0 IS DISABLED. EX0= 1 -> EXTERNAL INTERRUPT 0 IS ENABLED. ***** ****** * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * I-----I-----I-----I-----I-----I-----I-----I-----I * * I __ I I I I I I I I * ****** I EA I - I - I ES I ET1 I EX1 I ET0 I EX0 I * * I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I DIRECT ADDRESS BIT I I I * * I I I I I I I I I ***** ****** I AF I - I - I AC I AB I AA I A9 I A8 I ================================================= SERIAL PORT CONTROL REGISTER ================================================= SCON.7 -> SMO = SPECIFY THE SERIAL PORT MODE, AS FOOLOWS: SCON.6 -> SM1 = SPECIFY THE SERIAL PORT MODE, AS FOOLOWS: _____________________________________________________________________ I SM0 I SM1 I MODE I DESCRIPTION I BAUD RATE I I_______I_______I_______I_________________I_________________________I I 0 I 0 I 0 I SHIFT REGISTER I FR.osc./12 I I 0 I 1 I 1 I 8-BIT UART I VARIABLE I I 1 I 0 I 2 I 9-BIT UART I FR.osc/64 or FR.osc./32 I I___1___I___1___I___3___I_9-BIT__UART_____I___________VARIABLE______I SCON.5 -> SM2= ENABLES THE MULTIPROCESSOR COMUNICATION FEATURE IN MODES 2 & 3 IN MODE 2 OR 3, IF SM2 = 1 THEN RI WILL NOT BE ACTIVATED IF THE RECEIVED 9th DATA BIT (RB8) IS 0. IN MODE 1, IF SM2 = 1 THEN RI WILL NOT BE ACTIVATED IF A VALID STOP BIT WAS NOT RECEIVED. IN MODE O, SM2 SHOULD BE 0. SCON.4 -> REN = ENABLES SERIAL RECEPTION. REN = 1, SET BY SOFTWARE TO ENABLE RECEPTION. REN = 0, CLEAR BY SOFTWARE TO DISABLE RECEPTION. SCON.3 -> TB8 = THE 9tH DATA BIT THAT WILL BE TRANSMITTED IN MODES 2 AND 3. SET OR CLEAR BY SOFTWARE AS DESIRED. SCON.2 -> RB8 = THE 9tH DATA BIT THAT WAS RECEIVED IN MODES 2 AND 3. IN MODE 1, IF SM2 = 0, RB8 IS THE STOP BIT, THAT WAS RECEIVED. IN MODE 0, RB8 IS NOT USED. SCON.1 -> TI = TRANSMIT INTERRUPT FLAG. SET BY HARDWARE AT THE END OF THE 8th BIT TIME IN MODE 0, OR AT THE BEGINNING OF THE STOP BIT IN OTHER MODES, IN ANY SERIAL TRANSMISSION. MUST BE CLEARED BY SOFTWARE. SCON.0 -> RI = RECEIVE INTERRUPT FLAG. SET BY HARDWARE AT THE END OF THE 8th BIT TIME IN MODE 0, OR HALFWAY TROUGH THE STOP TIME BIT IN THE OTHER MODES, IN ANY SERIAL RECEPTION (EXCEPT SEE SM2). MUST BE CLEARED BY SOFTWARE. *** *** *** * * * * * * * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * * ** * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * * I I I I I I I I I * * * * * * * I SMO I SM1 I SM2 I REN I TB8 I RB8 I TI I RI I * * * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * ** I I I DIRECT ADDRESS BIT I I I * * * * * * I I I I I I I I I * * * * * * * * I 9F I 9E I 9D I 9C I 9B I 9A I 99 I 98 I *** *** *** * * *** **** * * ***** * * * * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * I B U F F E R R E G I S T E R I * ***** * * ***** I SERIAL PORT RECEIVER / TRANSMITTER I * * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * I I I DIRECT ADDRESS BYTE I I I * * * * * * I I I I I I I I I * * * * * * * I 99 I 99 I 99 I 99 I 99 I 99 I 99 I 99 I *** **** *** * =================================================== TIMER/COUNTER MODE CONTROL REGISTER =================================================== GATE -> GATING CONTROL WHEN SET. ____ TIMER/COUNTER "x" IS ENABLED ONLY WHILE "INTx" PIN IS HIGH AND "TRx" CONTROL PIN IS SET ("...x" = 0 or 1). _ WHEN CLEARWD TIMER "x" IS ENABLED WHENEVER "TRx" CONTROL BIT IS SET. C/T -> TIMER OR COUNTER SELECTOR. CLEARED FOR TIMER OPERATION (INPUT FROM INTERNAL SYSTEM CLOCK). SET FOR COUNTER OPERATION (INPUT FROM "Tx" INPUT PIN). ____________________________________________________________________________ M1 M0 OPERATING MODE ____________________________________________________________________________ 0 0 MCS-48 TIMER "TLx" SERVES AS FIVE-BIT PRESCALER. 0 1 16 BIT TIMER/COUNTER "THx" AND "TLx" ARE CASCADED: THERE IS NO PRESCALER. 1 0 8-BIT AUTO-RELOAD TIMER-COUNTER "THx" HOLDS A VALUE WHICH IS TO BE RELOADED INTO "TLx" EACH TIME IF OVERFLOWS. 1 1 (TIMER 0) TL0 IS AN 8-BIT TIMER COUNTER-CONTROLLED BY THE STANDART TIMER 0 CONTROL BITS. TH0 IS AN 8-BIT TIMER COUNTER-CONTROLLED BY TIMER 1 CONTROL BITS. 1 1 (TIMER 1) TIMER/COUNTER 1 STOPPED. ***** * * *** **** * ** ** * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * * * I I _ I I I I I I I * * * * * * * I GATEI C/T I M1 I M0 I GATEI C/T I M1 I M0 I * * * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * * I I I DIRECT ADDRESS BYTE I I I * * * * * * * I I I I I I I I I * * * * * * * I 89 I 89 I 89 I 89 I 89 I 89 I 89 I 89 I * * * *** **** T I M E R 1 I T I M E R 0 =============================================== TIMER/COUNTER CONTROL REGISTER =============================================== TCON.7 -> TF1 = TIMER 1 OVERFLOW FLAG. TF1 = 1, SET BY HARDWARE ON TIMER/COUNTER OVERFLOW. TF1 = 0, CLEARED BY HARDWARE WHEN PROCESSOR VECTORS TO INTERRUPT ROUTINE. TCON.6 -> TR1 = TIMER 1 RUN CONTROL BIT. TR1 = 1, SET BY SOFTWARE TO TURN TIMER/COUNTER ON. TR1 = 0, CLEARED BY SOFTWARE TO TURN TIMER/COUNTER OFF. TCON.5 -> TF0 = TIMER 0 OVERFLOW FLAG. TF0 = 1, SET BY HARDWARE ON TIMER/COUNTER OVERFLOW. TF0 = 0, CLEARED BY HARDWARE WHEN PROCESSOR VECTORS TO INTERRUPT ROUTINE. TCON.4 -> TR0 = TIMER 0 RUN CONTROL BIT. TR0 = 1, SET BY SOFTWARE TO TURN TIMER/COUNTER ON. TRO = 0, CLEARED BY SOFTWARE TO TURN TIMER/COUNTER OFF. TCON.3 -> IE1 = INTERRUPT 1 EDGE FLAG. IE1 = 1, SET BY HARDWARE WHEN EXTERNAL INTERRUPT EDGE DEDECTED. IE1 = 0, CLEARED WHEN INTERRUPT PROCESSED. TCON.2 -> IT1 = INTERRUPT 1 TYPE CONTROL BIT. SET/CLEARED BY SOFTWARE TO SPECIFY FALLING EDGE/LOW LEVEL TRIGGERED EXTERNAL INTERRUPTS. TCON.1 -> IE0 = INTERRUPT 0 EDGE FLAG. IE0 = 1, SET BY HARDWARE WHEN EXTERNAL INTERRUPT EDGE DEDECTED. IE0 = 0, CLEARED WHEN INTERRUPT PROCESSED. TCON.0 -> IT0 = INTERRUPT 0 TYPE CONTROL BIT. SET/CLEARED BY SOFTWARE TO SPECIFY FALLING EDGE/LOW LEVEL TRIGGERED EXTERNAL INTERRUPTS. ***** *** *** * * * * * * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * ** * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * * I TF1 I TR1 I TF0 I TR0 I IE1 I IT1 I IE0 I IT0 I * * * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * * * I I I DIRECT ADDRESS BIT I I I * * * * * ** I I I I I I I I I * * * * * * * I 8F I 8E I 8D I 8C I 8B I 8A I 89 I 88 I * *** *** * * ***** * * * * * * ** I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * I I I I T I M E R 1 I I I * ***** * * I I I I M S BYTE I I I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I DIRECT ADDRESS BYTEI I I * * * * I I I I I I I I I * * * * I 8D I 8D I 8D I 8D I 8D I 8D I 8D I 8D I ***** * * **** * * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * I I I I T I M E R 0 I I I * ***** * * I I I I M S BYTE I I I * * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * * I I I DIRECT ADDRESS BYTEI I I * * * * * I I I I I I I I I * * * **** I 8C I 8C I 8C I 8C I 8C I 8C I 8C I 8C I ***** * * * * ** I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I I T I M E R 1 I I I * * * * I I I I L S BYTE I I I * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * I I I DIRECT ADDRESS BYTE I I I * * * I I I I I I I I I * ***** * I 8B I 8B I 8B I 8B I 8B I 8B I 8B I 8B I ***** * **** * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I I T I M E R 0 I I I * * * * I I I I L S BYTE I I I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I DIRECT ADDRESS BYTE I I I * * * * I I I I I I I I I * ***** **** I 8A I 8A I 8A I 8A I 8A I 8A I 8A I 8A I ***** **** * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * ** I I I I I I I I I * * * * * I I I I I I I I I ***** * * * I-----I-----I-----I-----I-----I-----I-----I-----I * ** * I I I DIRECT ADDRESS BIT I I I * * * I I I I I I I I I * * * I 87 I 86 I 85 I 84 I 83 I 82 I 81 I 80 I * **** ***** * * * ** I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * * I I I I I I I I I * * * * I P1.7I P1.6I P1.5I P1.4I P1.3I P1.2I P1.1I P1.0I ***** * I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I DIRECT ADDRESS BIT I I I * * I I I I I I I I I * * I 97 I 96 I 95 I 94 I 93 I 92 I 91 I 90 I * * ***** ***** * * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * I I I I I I I I I * * * I A15 I A14 I A13 I A12 I A11 I A10 I A09 I A08 I ***** **** I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I DIRECT ADDRESS BIT I I I * * I I I I I I I I I * * I A7 I A6 I A5 I A4 I A3 I A2 I A1 I A0 I * ****** ***** ***** * * * I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I * * * I-----I-----I-----I-----I-----I-----I-----I-----I * * * I I I I I ____I ____I I I * * **** I RD I WR I T1 I T0 I INT1I INT0I TXD I RXD I ***** * I-----I-----I-----I-----I-----I-----I-----I-----I * * I I I DIRECT ADDRESS BIT I I I * * I I I I I I I I I * * I B7 I B6 I B5 I B4 I B3 I B2 I B1 I B0 I * ***** S F R BIT AND BYTE ADDRESSES RAM BYTE (MSB) (LSB) I------I------I------I------I------I------I------I------I F0H I F7 I F6 I F5 I F4 I F3 I F2 I F1 I F0 I B I------I------I------I------I------I------I------I------I E0H I E7 I E6 I E5 I E4 I E3 I E2 I E1 I E0 I ACC I------I------I------I------I------I------I------I------I D0H I CY I AC I F0 I RS1 I RS0 I OV I I P I PSW I D7 I D6 I D5 I D4 I D3 I D2 I D1 I D0 I I------I------I------I------I------I------I------I------I B8H I - I - I PT2 I PS I PT1 I PX1 I PT0 I PX0 I IP I I I BD I BC I BB I BA I B9 I B8 I I------I------I------I------I------I------I------I------I B0H I /RD I /RW I T1 I T0 I INT1 I INT0 I TxD I RxD I P3 I B7 I B6 I B5 I B4 I B3 I B2 I B1 I B0 I I------I------I------I------I------I------I------I------I A8H I /EA I - I - I ES I ET1 I EX1 I ET0 I EX0 I IE I AF I I I AC I AB I AA I A9 I A8 I I------I------I------I------I------I------I------I------I A0H I I I I I I I I I P2 I------I------I------I------I------I------I------I------I 99H I I I I I I I I I SBUF I------I------I------I------I------I------I------I------I 98H I SM0 I SM1 I SM2 I REN I TB8 I RB8 I TI I RI I SCON I 9F I 9E I 9D I 9C I 9B I 9A I 99 I 98 I I------I------I------I------I------I------I------I------I 90H I I I I I I I I I P1 I------I------I------I------I------I------I------I------I 8DH I I I I I I I I I TH1 I------I------I------I------I------I------I------I------I 8CH I I I I I I I I I TH0 I------I------I------I------I------I------I------I------I 8BH I I I I I I I I I TL1 I------I------I------I------I------I------I------I------I 8AH I I I I I I I I I TL0 I------I------I------I------I------I------I------I------I 89H I GATE1I C/T| I M1 I M0 I GATE0I C/T| I M1 I M0 I TMOD I------I------I------I------I------I------I------I------I 88H I TF1 I TR1 I TF0 I TR0 I IE1 I IT1 I IE0 I IT0 I TCON I 8F I 8E I 8D I 8C I 8B I 8A I 89 I 88 I I------I------I------I------I------I------I------I------I 87H I SMOD I - I - I - I GF1 I GF0 I PD I IDL I PCON I------I------I------I------I------I------I------I------I 83H I I I I I I I I I DPH I------I------I------I------I------I------I------I------I 82H I I I I I I I I I DPL I------I------I------I------I------I------I------I------I 81H I I I I I I I I I SP I------I------I------I------I------I------I------I------I 80H I I I I I I I I I P0 I------I------I------I------I------I------I------I------I R A M BIT ADDRESSES RAM BYTE (MSB) (LSB) 7F H I------I------I------I------I------I------I------I------I 127 I I = = I I I------I------I------I------I------I------I------I------I 2F H I 7F I 7E I 7D I 7C I 7B I 7A I 79 I 78 I 47 I------I------I------I------I------I------I------I------I 2E H I 77 I 76 I 75 I 74 I 73 I 72 I 71 I 70 I 46 I------I------I------I------I------I------I------I------I 2D H I 6F I 6E I 6D I 6C I 6B I 6A I 69 I 68 I 45 I------I------I------I------I------I------I------I------I 2C H I 67 I 66 I 65 I 64 I 63 I 62 I 61 I 60 I 44 I------I------I------I------I------I------I------I------I 2B H I 5F I 5E I 5D I 5C I 5B I 5A I 59 I 58 I 43 I------I------I------I------I------I------I------I------I 2A H I 57 I 56 I 55 I 54 I 53 I 52 I 51 I 50 I 42 I------I------I------I------I------I------I------I------I 29 H I 4F I 4E I 4D I 4C I 4B I 4A I 49 I 48 I 41 I------I------I------I------I------I------I------I------I 28 H I 47 I 46 I 45 I 44 I 43 I 42 I 41 I 40 I 40 I------I------I------I------I------I------I------I------I 27 H I 3F I 3E I 3D I 3C I 3B I 3A I 39 I 38 I 39 I------I------I------I------I------I------I------I------I 26 H I 37 I 36 I 35 I 34 I 33 I 32 I 31 I 30 I 38 I------I------I------I------I------I------I------I------I 25 H I 2F I 2E I 2D I 2C I 2B I 2A I 29 I 28 I 37 I------I------I------I------I------I------I------I------I 26 H I 27 I 26 I 25 I 24 I 23 I 22 I 21 I 20 I 36 I------I------I------I------I------I------I------I------I 23 H I 1F I 1E I 1D I 1C I 1B I 1A I 19 I 18 I 35 I------I------I------I------I------I------I------I------I 22 H I 17 I 16 I 15 I 14 I 13 I 12 I 11 I 10 I 34 I------I------I------I------I------I------I------I------I 21 H I 0F I 0E I 0D I 0C I 0B I 0A I 09 I 08 I 33 I------I------I------I------I------I------I------I------I 20 H I 07 I 06 I 05 I 04 I 03 I 02 I 01 I 00 I 32 ----------I------I------I------I------I------I------I------I------I-------- 1F H I I 31 I BANK 3 I 18 H I I 24 ----------I------I------I------I------I------I------I------I------I-------- 17 H I I 23 I BANK 2 I 10 H I I 16 ----------I------I------I------I------I------I------I------I------I-------- 0F H I I 15 I BANK 1 I 08 H I I 8 ----------I------I------I------I------I------I------I------I------I-------- 07 H I I 7 I BANK 0 I 00 H I I 0 ----------I------I------I------I------I------I------I------I------I-------- ______________________ I (_____) I P1.0 <--->I 1 40 I----- Ucc I I I I P1.1 <--->I 2 39 I<---> P0.0 / AD0 I I I I P1.2 <--->I 3 38 I<---> P0.1 / AD1 I I I I P1.3 <--->I 4 MICRO 37 I<---> P0.2 / AD2 I I I I P1.4 <--->I 5 CONTROLLER 36 I<---> P0.3 / AD3 I I I I P1.5 <--->I 6 8051 35 I<---> P0.4 / AD4 I I I I P1.6 <--->I 7 34 I<---> P0.5 / AD5 I I I I P1.7 <--->I 8 33 I<---> P0.6 / AD6 I I I I RST / Upd --->I 9 32 I<---> P0.7 / AD7 I I __ RxD ----> P3.0 <--->I 10 31 I<---- EA / Udd I I I I ____ TxD <---- P3.1 <--->I 11 30 I----> ALE / PROG I I ____ I I ____ INTO ----> P3.2 <--->I 12 29 I----> PSEN I I ____ I I INT1 ----> P3.3 <--->I 13 28 I<---> P2.7 / AD15 I I I I T0 ----> P3.4 <--->I 14 27 I<---> P2.6 / AD14 I I I I T1 ----> P3.5 <--->I 15 26 I<---> P2.5 / AD13 I I __ I I WR <---- P3.6 <--->I 16 25 I<---> P2.4 / AD12 I I __ I I RD <---- P3.7 <--->I 17 24 I<---> P2.3 / AD11 I I I I XTAL2 <----I 18 23 I<---> P2.2 / AD10 I I I I XTAL1 ---->I 19 22 I<---> P2.1 / AD9 I I I I GND -----I 20 21 I<---> P2.0 / AD8 I____________________I ARITHMETIC OPERATION ADD A,Rr ADD REGISTER TO A ADD A,DIRECT ADD DIRECT BYTE TO A ADD A,@Ri ADD INDIRECT RAM TO A ADD A,#DATA ADD IMMEDIATE DATA TO A ADDC A,Rr ADD REGISTER TO A WITH CARRY FLAG ADDC A,DIRECT ADD DIRECT BYTE TO A WITH CARRY FLAG ADDC A,@Ri ADD INDIRECT RAM TO A WITH CARRY FLAG ADDC A,#DATA ADD IMMEDIATE DATA TO A WITH CARRY FLAG SUBB A,Rr SUBTRACT REGISTER FROM A WITH BOOROW SUBB A,DIRECT SUBTRACT DIRECT BYTE FROM A WITH BORROW SUBB A,@Ri SUBTRACT INDIRECT RAM FROM A WITH BOOROW SUBB A,#DATA SUBTRACT IMMEDIATE DATA FROM A WITH BORROW INC A INCREMENT A INC Rr INCREMENT REGISTER INC DIRECT INCREMENT DIRECT BYTE INC @Rr INCREMENT INDIRECT RAM DEC A DECREMENT A DEC Rr DECREMENT REGISTER DEC DIRECT DECREMENT DIRECT BYTE DEC @Rr DECREMENT INDIRECT RAM INC DPTR INCREMENT DATA POINTER MUL AB MULTIPLY A & B DIV AB DIVIDE A BY B DA A DECIMAL ADJUST A LOGIC OPERATION ANL A,Rr AND REGISTER TO A ANL A,DIRECT AND DIRECT BYTE TO A ANL A,@Ri AND INDIRECT RAM TO A ANL A,#DATA AND IMMEDIATE DATA TO A ANL DIRECT,A AND A TO DIRECT BYTE ANL DIRECT,#DATA AND IMMEDIATE DATA TO DIRECT BYTE ORL A,Rr OR REGISTER TO A ORL A,DIRECT OR DIRECT BYTE TO A ORL A,@Ri OR INDIRECT RAM TO A ORL A,#DATA OR IMMEDIATE DATA TO A ORL DIRECT,A OR A TO DIRECT BYTE ORL DIRECT,#DATA OR IMMEDIATE DATA TO DIRECT BYTE XRL A,Rr EXCLUSIVE-OR REGISTER TO A ORL A,DIRECT EXCLUSIVE-OR DIRECT BYTE TO A ORL A,@Ri EXCLUSIVE-OR INDIRECT RAM TO A ORL A,#DATA EXCLUSIVE-OR IMMEDIATE DATA TO A ORL DIRECT,A EXCLUSIVE-OR A TO DIRECT BYTE ORL DIRECT,#DATA EXCLUSIVE-OR IMMEDIATE DATA TO DIRECT BYTE CLR A CLEAR A CPL A COMPLEMENT A RL A ROTATE A LEFT RLC A ROTATE A LEFT THROUGH THE CARRY FLAG RR A ROTATE A RIGHT RRC A ROTATE A RIGHT THROUGH THE CARRY FLAG SWAP A SWAP NIBBLES WITHIN A BOOLEAN VARIABLE MANIPULATION CLR C CLEAR CARRY FLAG CLR BIT CLEAR DIRECT BIT SETB C SET CARRY FLAG SETB BIT SET DIRECT BIT CPL C COMPLEMENT CARRY FLAG CPL BIT COMPLEMENT DIRECT BIT ANL C,BIT AND DIRECT BIT TO CARRY FLAG ANL C,/BIT AND COMPLEMENT OF DIRECT BIT TO CARRY FLAG ORL C,BIT OR DIRECT BIT TO CARRY FLAG ORL C,/BIT OR COMPLEMENT OF DIRECT BIT TO CARRY FLAG MOV C,BIT MOVE DIRECT BIT TO CARRY FLAG MOV BIT,C MOVE CARRY FLAG TO DIRECT BIT DATA TRANSFER MOV A,Rr MOVE REGISTER TO A MOV A,DIRECT MOVE DIRECT BYTE TO A MOV A,@Ri MOVE INDIRECT RAM TO A MOV A,#DATA MOVE IMMEDIATE DATA TO A MOV Rr,A MOVE A TO REGISTER MOV Rr,DIRECT MOVE DIRECT BYTE TO REGISTER MOV Rr,#DATA MOVE IMMEDIATE DATA TO REGISTER MOV DIRECT,A MOVE A TO DIRECT BYTE MOV DIRECT,Rr MOVE REGISTER TO DIRECT BYTE MOV DIRECT,DIRECT MOVE DIRECT BYTE TO DIRECT MOV DIRECT,@Ri MOVE INDIRECT RAM TO DIRECT BYTE MOV DIRECT,#DATA MOVE IMMEDIATE DATA TO DIRECT BYTE MOV @Ri,A MOVE A TO INDIRECT RAM MOV @Ri,DIRECT MOVE DIRECT BYTE TO INDIRECT RAM MOV @Rr,#DATA MOVE IMMEDIATE DATA TO INDERECT RAM MOV DPTR,#DATA16 LOAD DATA POINTER WITH A 16-BIT CONSTANT MOVC A,@A+DPTR MOVE CODE BYTE RELATIVE TO DPTR TO A MOVC A,@A+PC MOVE CODE BYTE RELATIVE TO PC TO A MOVX A,@Ri MOVE EXTERNAL RAM (8-BIT ADDRESS) TO A MOVX A,@DPTR MOVE EXTERNAL RAM (16-BIT ADDRESS) TO A MOVX @Ri,A MOVE A TO EXTERNAL RAM (8-BIT ADDRESS) MOVX @DPTR,A MOVE A TO EXTERNAL RAM (16-BIT ADDRESS) PUSH DIRECT PUSH DIRECT BYTE INTO STACK POP DIRECT POP DIRECT BYTE FROM STACK XCH A,Rr EXCHANGE REGISTER WITH A XCH A,DIRECT EXCHANGE DIRECT BYTE WITH A XCH A,@Ri EXCHANGE INDIRECT RAM WITH A XCHD A,@Rr EXCHANGE LOW-ORDER DIGIT INDIRECT RAM WITH A PROGRAM AND MASHINE CONTROL ACALL addr11 ABSOLUTE SUBROUTINE CALL LCALL addr16 LONG SUBROUTINE CALL RET RETURN FROM SUBROUTINE RETI RETURN FROM INTERRUPT AJMP addr11 ABSOLUTE JUMP LJMP addr16 LONG JUMP SJMP REL SHORT JUMP (RELATIVE ADDRESS) JMP @A+DPTR JUMP INDIRECT RELATIVE TO THE DPTR JZ REL JUMP IF A IS ZERO JNZ REL JUMP IF A IS NOT ZERO JC REL JUMP IF CARRY FLAG IS SET JNC REL JUMP IF NO CARRY FLAG JB BIT,REL JUMP IF DIRECT BIT IS SET JNB BIT,REL JUMP IF DIRECT BIT IS NOT SET JBC BIT,REL JUMP IF DIRECT BIT IS SET AND CLEAR BIT CJNE A,DIRECT,REL COMPARE DIRECT TO A AND JAMP IF NOT EQUAL CJNE A,#DATA,REL COMPARE IMMEDIATE TO A AND JAMP IF NOT EQUAL CJNE Rr,#DATA,REL COMPARE IMMEDIATE TO REGISTER AND JAMP IF NOT EQUAL CJNE @Rr,#DATA,REL COMPARE IMMED. TO INDIRECT RAM AND JAMP IF NOT EQUAL DJNZ Rr,REL DECREMENT REGISTER AND JUMP IF NOT ZERO DJNZ Rr,REL DECREMENT DIRECT AND JUMP IF NOT ZERO NOP NO OPERATION LO 0 1 2 3 4 5 6 7 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ HI ! NOP ! AJMP ! LJMP ! RR ! INC ! INC ! INC ! INC * 0 ! ! Pg0 ! a16 ! A ! A ! d ! @R0 ! @R1 * ! 1/1 ! 2/2 ! 3/2 ! 1/1 ! 1/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JBC ! ACALL ! LCALL ! RRC ! DEC ! DEC ! DEC ! DEC * 1 ! b,r ! Pg0 ! a16 ! A ! A ! d ! @R0 ! @R1 * ! 3/2 ! 2/2 ! 3/2 ! 1/1 ! 1/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JB ! AJMP ! RET ! RL ! ADD ! ADD ! ADD ! ADD * 2 ! b,r ! Pg1 ! ! A ! A,# ! A,d ! A,@R0 ! A,@R1 * ! 3/2 ! 2/2 ! 1/2 ! 1/1 ! 2/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JNB ! ACALL ! RETI ! RLC ! ADDC ! ADDC ! ADDC ! ADDC * 3 ! b,r ! Pg1 ! ! A ! A,# ! A,d ! A,@R0 ! A,@R1 * ! 3/2 ! 2/2 ! 1/2 ! 1/1 ! 2/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JC ! AJMP ! ORL ! ORL ! ORL ! ORL ! ORL ! ORL * 4 ! r ! Pg2 ! d,A ! d,# ! A,# ! A,d ! A,@R0 ! A,@R1 * ! 2/2 ! 2/2 ! 2/1 ! 3/2 ! 2/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JNC ! ACALL ! ANL ! ANL ! ANL ! ANL ! ANL ! ANL * 5 ! r ! Pg2 ! d,A ! d,# ! A,# ! A,d ! A,@R0 ! A,@R1 * ! 2/2 ! 2/2 ! 2/1 ! 3/2 ! 2/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JZ ! AJMP ! XRL ! XRL ! XRL ! XRL ! XRL ! XRL * 6 ! r ! Pg3 ! d,A ! d,# ! A,# ! A,d ! A,@R0 ! A,@R1 * ! 2/2 ! 2/2 ! 2/1 ! 3/2 ! 2/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! JNZ ! ACALL ! ORL ! JMP ! MOV ! MOV ! MOV ! MOV * 7 ! r ! Pg3 ! C,b ! @A+DP ! A,# ! d,# ! @R0,# ! @R1,# * ! 2/2 ! 2/2 ! 2/2 ! 1/2 ! 2/1 ! 3/2 ! 2/1 ! 2/1 * LO 0 1 2 3 4 5 6 7 * LO 0 1 2 3 4 5 6 7 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! SJMP ! AJMP ! ANL ! MOVC ! DIV ! MOV ! MOV ! MOV * 8 ! r ! Pg4 ! C,b ! A,A+P ! AB ! d,d ! d,@R0 ! d,@R1 * ! 2/2 ! 2/2 ! 2/2 ! 1/2 ! 1/4 ! 3/2 ! 2/2 ! 2/2 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! MOV ! ACALL ! MOV ! MOVC ! SUBB ! SUBB ! SUBB ! SUBB * 9 ! D,#16 ! Pg4 ! b,C ! A,A+D ! A,# ! A,d ! A,@R0 ! A,@R1 * ! 3/2 ! 2/2 ! 2/2 ! 1/2 ! 2/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! ORL ! AJMP ! MOV ! INC ! MUL ! ! MOV ! MOV * A ! C,/b ! Pg5 ! C,b ! DPTR ! A ! ! @R0,d ! @R1,d * ! 2/2 ! 2/2 ! 2/1 ! 1/2 ! 1/4 ! ! 2/2 ! 2/2 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! ANL ! ACALL ! CPL ! CPL ! CJNE ! CJNE ! CJNE ! CJNE * B ! C,/b ! Pg5 ! b ! C ! A,#,r ! A,d,r ! @R0#r ! @R1#r * ! 2/2 ! 2/2 ! 2/1 ! 1/1 ! 3/2 ! 3/2 ! 3/2 ! 3/2 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! PUSH ! AJMP ! CLR ! CLR ! SWAP ! XCH ! XCH ! XCH * C ! d ! Pg6 ! b ! C ! A ! A,d ! A,@R0 ! A,@R1 * ! 2/2 ! 2/2 ! 2/1 ! 1/1 ! 1/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! POP ! ACALL ! SETB ! SETB ! DA ! DJNZ ! XCHD ! XCHD * D ! d ! Pg6 ! b ! C ! A ! d,r ! A,@R0 ! A,@R1 * ! 2/2 ! 2/2 ! 2/1 ! 1/1 ! 1/1 ! 3/2 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! MOVX ! AJMP ! MOVX ! MOVX ! CLR ! MOV ! MOV ! MOV * E ! A,@DP ! Pg7 ! A,@R0 ! A,@R1 ! A ! A,d ! A,@R0 ! A,@R1 * ! 1/2 ! 2/2 ! 1/2 ! 1/2 ! 1/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ ! MOVX ! ACALL ! MOVX ! MOVX ! CPL ! MOV ! MOV ! MOV * F ! @DP,A ! Pg7 ! @R0,A ! @R1,A ! A ! d,A ! @R0,A ! @R1,A * ! 1/2 ! 2/2 ! 1/2 ! 1/2 ! 1/1 ! 2/1 ! 1/1 ! 1/1 * -----+--------+--------+--------+--------+--------+--------+--------+--------+ LO 0 1 2 3 4 5 6 7 * LO * 8 9 A B C D E F -----+--------+--------+--------+--------+--------+--------+--------+--------+ HI * INC ! INC ! INC ! INC ! INC ! INC ! INC ! INC ! 0 * R0 ! R1 ! R2 ! R3 ! R4 ! R5 ! R6 ! R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * DEC ! DEC ! DEC ! DEC ! DEC ! DEC ! DEC ! DEC ! 1 * R0 ! R1 ! R2 ! R3 ! R4 ! R5 ! R6 ! R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * ADD ! ADD ! ADD ! ADD ! ADD ! ADD ! ADD ! ADD ! 2 * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * ADDC ! ADDC ! ADDC ! ADDC ! ADDC ! ADDC ! ADDC ! ADDC ! 3 * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * ORL ! ORL ! ORL ! ORL ! ORL ! ORL ! ORL ! ORL ! 4 * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * ANL ! ANL ! ANL ! ANL ! ANL ! ANL ! ANL ! ANL ! 5 * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * XRL ! XRL ! XRL ! XRL ! XRL ! XRL ! XRL ! XRL ! 6 * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! 7 * R0,# ! R1,# ! R2,# ! R3,# ! R4,# ! R5,# ! R6,# ! R7,# ! * 2/1 ! 2/1 ! 2/1 ! 2/1 ! 2/1 ! 2/1 ! 2/1 ! 2/1 ! LO * 8 9 A B C D E F LO * 8 9 A B C D E F -----+--------+--------+--------+--------+--------+--------+--------+--------+ * MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! 8 * d,R0 ! d,R1 ! d,R2 ! d,R3 ! d,R4 ! d,R5 ! d,R6 ! d,R7 ! * 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * SUBB ! SUBB ! SUBB ! SUBB ! SUBB ! SUBB ! SUBB ! SUBB ! 9 * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! A * R0,d ! R1,d ! R2,d ! R3,d ! R4,d ! R5,d ! R6,d ! R7,d ! * 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * CJNE ! CJNE ! CJNE ! CJNE ! CJNE ! CJNE ! CJNE ! CJNE ! B * 0,#,r ! 1,#,r ! 2,#,r ! 3,#,r ! 4,#,r ! 5,#,r ! 6,#,r ! 7,#,r ! * 3/2 ! 3/2 ! 3/2 ! 3/2 ! 3/2 ! 3/2 ! 3/2 ! 3/2 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * XCH ! XCH ! XCH ! XCH ! XCH ! XCH ! XCH ! XCH ! C * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * DJNZ ! DJNZ ! DJNZ ! DJNZ ! DJNZ ! DJNZ ! DJNZ ! DJNZ ! D * R0,r ! R1,r ! R2,r ! R3,r ! R4,r ! R5,r ! R6,r ! R7,r ! * 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! 2/2 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! E * A,R0 ! A,R1 ! A,R2 ! A,R3 ! A,R4 ! A,R5 ! A,R6 ! A,R7 ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! -----+--------+--------+--------+--------+--------+--------+--------+--------+ * MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! MOV ! F * R0,A ! R1,A ! R2,A ! R3,A ! R4,A ! R5,A ! R6,A ! R7,A ! * 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! 1/1 ! --------+-----+--------+--------+--------+--------+--------+--------+--------+ LO * 8 9 A B C D E F