- Generated on Mon Jun 9 2014 14:43:20 for MLC interface driver by
1.8.7
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MLC interface driver
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| #define BASE_ADDRESS 0x00004000 |
Base address of ZONE0, address 0x0000 from outer world
Base address of EMIF nCS1, address 0x00000000 from outer world
Definition at line 228 of file MLC_drv.h.
Referenced by MLC_DMA_enable_isr(), MLC_read(), and MLC_write().
| #define BASE_ADDRESS 0x60000000u |
| #define EXT_FAULTS_ADDR (EXT_MOD_OFFSET + 0x0017) |
Address of FAULT register.
Definition at line 53 of file MLC_ext_module.h.
| #define EXT_MOD_OFFSET 0x0100 |
Basic offset of adresses of external FPGA module
Definition at line 34 of file MLC_ext_module.h.
| #define EXT_RESERVED_12 (EXT_MOD_OFFSET + 0x0012) |
Reserved for future use of basic FPGA design.
Definition at line 47 of file MLC_ext_module.h.
| #define EXT_RESERVED_13 (EXT_MOD_OFFSET + 0x0013) |
Reserved for future use of basic FPGA design.
Definition at line 48 of file MLC_ext_module.h.
| #define EXT_RESERVED_14 (EXT_MOD_OFFSET + 0x0014) |
Reserved for future use of basic FPGA design.
Definition at line 49 of file MLC_ext_module.h.
| #define EXT_RESERVED_15 (EXT_MOD_OFFSET + 0x0015) |
Reserved for future use of basic FPGA design.
Definition at line 50 of file MLC_ext_module.h.
| #define EXT_RESERVED_16 (EXT_MOD_OFFSET + 0x0016) |
Reserved for future use of basic FPGA design.
Definition at line 51 of file MLC_ext_module.h.
| #define EXT_RESERVED_18 (EXT_MOD_OFFSET + 0x0018) |
Reserved for future use of basic FPGA design.
Definition at line 55 of file MLC_ext_module.h.
| #define EXT_RESERVED_19 (EXT_MOD_OFFSET + 0x0019) |
Reserved for future use of basic FPGA design.
Definition at line 56 of file MLC_ext_module.h.
| #define EXT_RESERVED_1A (EXT_MOD_OFFSET + 0x001A) |
Reserved for future use of basic FPGA design.
Definition at line 57 of file MLC_ext_module.h.
| #define EXT_RESERVED_1B (EXT_MOD_OFFSET + 0x001B) |
Reserved for future use of basic FPGA design.
Definition at line 58 of file MLC_ext_module.h.
| #define EXT_RESERVED_1C (EXT_MOD_OFFSET + 0x001C) |
Reserved for future use of basic FPGA design.
Definition at line 59 of file MLC_ext_module.h.
| #define EXT_RESERVED_1D (EXT_MOD_OFFSET + 0x001D) |
Reserved for future use of basic FPGA design.
Definition at line 60 of file MLC_ext_module.h.
| #define EXT_RESERVED_1E (EXT_MOD_OFFSET + 0x001E) |
Reserved for future use of basic FPGA design.
Definition at line 61 of file MLC_ext_module.h.
| #define EXT_RESERVED_1F (EXT_MOD_OFFSET + 0x001F) |
Reserved for future use of basic FPGA design.
Definition at line 62 of file MLC_ext_module.h.
| #define FPGA_FAULTS_ADDR 0x0017 |
| #define FPGA_LEDS_SHOW_DATA 0x0000 |
| #define FPGA_LEDS_SHOW_PWMA 0x0100 |
| #define FPGA_LEDS_SHOW_PWMB 0x0200 |
| #define FPGA_LEDS_SHOW_PWMC 0x0300 |
| #define FPGA_LEDS_SHOW_PWMD 0x0400 |
| #define FPGA_LEDS_SHOW_PWME 0x0500 |
| #define FPGA_LEDS_SHOW_PWMF 0x0600 |
| #define FPGA_RESERVED_13 0x0013 |
| #define FPGA_RESERVED_14 0x0014 |
| #define FPGA_RESERVED_15 0x0015 |
| #define FPGA_RESERVED_16 0x0016 |
| #define FPGA_RESERVED_18 0x0018 |
| #define FPGA_RESERVED_19 0x0019 |
| #define FPGA_RESERVED_1A 0x001A |
| #define FPGA_RESERVED_1B 0x001B |
| #define FPGA_RESERVED_1C 0x001C |
| #define FPGA_RESERVED_1D 0x001D |
| #define FPGA_RESERVED_1E 0x001E |
| #define FPGA_RESERVED_1F 0x001F |
| #define READ_AD1 0x0001 |
Offset of XINTF location of AD CH1 read channel
Definition at line 243 of file MLC_drv.h.
Referenced by MLC_ADC1_read(), MLC_ADC_read(), and MLC_DMA_enable_isr().
| #define READ_AD2 0x0002 |
Offset of XINTF location of AD CH2 read channel
Definition at line 244 of file MLC_drv.h.
Referenced by MLC_ADC2_read(), and MLC_ADC_read().
| #define READ_AD3 0x0003 |
Offset of XINTF location of AD CH2 read channel
Definition at line 245 of file MLC_drv.h.
Referenced by MLC_ADC3_read(), and MLC_ADC_read().
| #define READ_ARC 0x0005 |
| #define READ_EXT_VER (EXT_MOD_OFFSET + 0x0010) |
Offset of XINTF location of FPGA firmware version register of external module
Definition at line 36 of file MLC_ext_module.h.
Referenced by MLC_init().
| #define READ_FPGA_VER 0x0010 |
| #define READ_HV_INPUT 0x0004 |
| #define READ_PCB_REV 0x000F |
| #define READ_UIO 0x0009 |
| #define READ_VER 0x0000 |
| #define RW_CS_EXT1 0x0006 |
| #define RW_CS_EXT2 0x0007 |
| #define RW_CS_EXT3 0x0008 |
| #define RW_EXT_LED_REG (EXT_MOD_OFFSET + 0x0011) |
External FPGA LED register offset definition. Register is splitted to two parts: bits 15-8 are configuration, 7-0 are data to show. Configuration data says which data will LEDs show. See FPGA_LEDS... constants. Currently showing of data form lower byte of this register and all PWM gates are supported by FPGA firmware 0.1 and higher.
Definition at line 45 of file MLC_ext_module.h.
Referenced by MLC_init().
| #define RW_FPGA_LED_REG 0x0011 |
FPGA LED register offset definition. Register is splitted to two parts: bits 15-8 are configuration, 7-0 are data to show. Configuration data says which data will LEDs show. See FPGA_LEDS... constants. Currently showing of data form lower byte of this register and all PWM gates are supported by FPGA demo firmware 3.2 and higher.
| #define RW_UIO 0x0009 |
| #define RW_UIO_CONF 0x000A |
| #define WRITE_AD_CONF 0x0000 |
Offset of XINTF location of ADC configuration register
Definition at line 235 of file MLC_drv.h.
Referenced by MLC_ADC_setup(), and MLC_ADC_setup_SOC().
| #define WRITE_CLRRES_AD 0x0003 |
Offset of XINTF location of ADC reset signal to set to inactive state
Definition at line 238 of file MLC_drv.h.
Referenced by MLC_ADC_reset().
| #define WRITE_DBGLEDS 0x0004 |
Offset of XINTF location of debug LEDs/pins output register
Definition at line 239 of file MLC_drv.h.
Referenced by MLC_DBG_clear(), and MLC_DBG_set().
| #define WRITE_LCD_DISP 0x0012 |
FPGA LCD register offset definition. Register is splitted to two parts: high byte is position where character passed as low byte will be printed.Offset of XINTF location of LCD write register
Definition at line 278 of file MLC_drv.h.
Referenced by MLC_LCD_clrscr(), MLC_LCD_write_str(), and MLC_LCD_write_to().
| #define WRITE_PWR_OUT 0x0001 |
Offset of XINTF location of PWR out output register
Definition at line 236 of file MLC_drv.h.
Referenced by MLC_PWR_off(), and MLC_PWR_on().
| #define WRITE_SETRES_AD 0x0002 |
Offset of XINTF location of ADC reset signal to set to active state
Definition at line 237 of file MLC_drv.h.
Referenced by MLC_ADC_reset().
1.8.7